Welcome to FPGA Interchange documentation!

Contents:

• Device Resources
  • Terminology
  • The place and route problem
  • Site example
  • Details
  • Additional topics
• Cell, BEL and Site Design
  • Assumptions about cell placement and driver BEL pins
  • Granularity of the cell library
  • Drawing site boundaries
  • Drawing BEL boundaries
  • Static routing muxes and bitstream formats
• Pseudo Cells
  • Example
  • Future enhancements

Indices and tables

• Index

• Module Index

• Search Page